Various types of radiation such as neutrons and alpha particles can directly or indirectly cause soft errors in memories. The error rate goes up as device size decreases and as memory size increases. For a cache based system with a unified second level cache, the error could be either in data, instructions or direct memory access (DMA) transfer data. An error in an instruction can cause unexpected behavior in the data processor. Having the ability to correct such an instruction before it reaches the central processing unit (CPU) can prevent this behavior. CPU and DMA data have components which remain static for a long time making them susceptible to these soft errors. This data needs to be protected against corruption due from soft errors. Typically, this data remains in the level 2 cache for long durations. Protecting data at this level of the memory hierarchy is most effective.
The information required for this protection depends on the type of detection/correction required. Complete data correction requires a lot of information. This may can prove costly in terms of area and memory bits. Efficient implementation of the generation and decode of this information is required for high performance devices.